In order to read, write and erase the EEPROM, it is necessary to apply the first positive potential necessary for reading, the second positive potential necessary for writing and a negative potential necessary for erasing to the memory cell.
FIG. 1 shows a part of a decoding circuit of an EEPROM disclosed in Japanese Patent Kokai 5-28784, which is provided with a voltage-switching circuit having the function mentioned in the above. In this EEPROM, although a method for applying a negative potential to the gate of the memory cell transistor at the time of erase mode is adopted, there is no necessity for continuously operating a negative potential supply circuit, and the circuit structure of the word line driver is simplified.
As shown in FIG. 1, the gates of the memory cell transistors 11 are connected by a word line 12, and drains of the memory cell transistors 11 are connected by a bit line 13. Moreover, sources of the memory cell transistors 11 are connected by a source line 14. In the aforementioned memory cell array, the first positive potential (5V, for instance) is applied to the selected word line 12 and an intermediate read potential (1V, for instance) is applied to the selected bit line 13 at the time of read. At the time of write, the second positive potential (12V, for instance) is applied to the selected word line. Moreover, at the tie of erase, the first positive potential (5V, for instance) is applied to the source line 14, and a negative potential (-10V, for instance) is applied to the selected word line 12.
However, since the negative potential-generating circuit 10 shown in FIG. 1 used in the conventional EEPROM supplies the negative potential at the time of erase mode and the ground potential at the times of the other modes, it is not suited for erase verify mode.